1. Field of the Invention
This invention relates to a structure of MOS ESD (electrostatic discharge) protection circuit. And more specifically, this invention relates to a MOS ESD protection circuit that minimizes heating effect by embedded well diode.
2. Description of the Prior Art
Electrostatic discharge phenomena in integrated circuits have grown in importance as technologies shrink to below 0.5 microns and the number of transistors on a single chip approach the 5 million mark. The high voltages result in large electrical fields and high current densities in the small devices that can lead to breakdown of insulators and thermal damage in the integrated circuits. Therefore, ESD protection circuit is necessary for integrated circuits and then introduction of each new generation of semiconductor technology results in new challenges in terms of ESD capability and protection circuit design.
The relation between other parts of integrated circuits and an ESD protection circuit that used to protect chips from external charge/voltage is shown in FIG. 1. As FIG. 1 shows, external current (charger) is conducted from terminal 10 through internal buffer 12 to internal chips 13, and internal current (charger) is conducted from internal chips 13 through internal buffer 12 to terminal 10. However, because larger external current will induce unexpected damage on internal chips 13, ESD protection circuits 11 are used where ESD protection circuits 11 are located between terminal 10 and internal buffer 12. Moreover, ESD protection circuits 11 are turn-off when no larger external current is appeared, and when larger external current appears ESD protection circuits 11 are turned on automatically. Therefore, larger external current is conducted to VDD 14 and VSS 15, and internal chips 13 are not damaged.
There are many varieties of ESD protect circuit, and one useful variety of ESD protection circuits is the metal-oxide-semiconductor (MOS) protect circuit that uses MOS transistor to form required ESD protection circuit. Herein, advantages of MOS ESD protection circuit include high integration and high reliability. Significantly, when integration of integrated circuits are increased, MOS ESD protection circuit is more attractive for it can reduce occupied area of ESD protection circuit to further increase integration.
As the cross-sectional figure shown in FIG. 2A where conventional structure of MOS ESD protection circuit is qualitative illustrated. The MOS ESD protection circuit is form in and on well 22, and is surrounded by isolation 21 to prevent the protection circuit is interfered with other parts of substrate 20. Herein, a plurality of MOS transistors are located in and on well 22, and these MOS transistors are surrounded by guard ring 26. Moreover, drains 24 are coupled to terminal 27 by first conductive lines 28, and sources 23, gates 25 and guard ring 26 are coupled to relative ground point 295 by second conductive line 29. Beside, conventional layout of MOS ESD protection circuit is qualitative illustrated in FIG. 2B, where FIG. 2A is a cross-sectional illustration along AA line. Moreover, relative ground point 295 usually is provided by substrate 20.
Mechanism of the MOS ESD protection circuit can briefly described as following: when chargers is appeared on terminal 27 and more then threshold value of the MOS ESD protection circuit, they are conducted to drains 24 by first conductive lines 28. Then, owing to the fact extra charges induce electrical field and alter distribution of charge carriers inside substrate 20 and well 22, some parasitic bipolar junction transistors that located under drains 24 and sources 23 are formed, and then extra chargers are conducted grounded point 295. One advantages of MOS ESD protection circuit is that current gain of bipolar junction transistors can enhance the protect ability of ESD protection circuit. Moreover, numerous parasitic diodes are formed under gates 25. Thus, though trigger time of bipolar junction transistors is slow, before parasitic bipolar junction transistors are triggered, extra chargers also are conducted to grounded point 295 by parasitic diodes and first conductive lines 29.
However, an unavoidable deficiency of conventional MOS ESD protection circuit is that parasitic diodes induce a large electrical field on depletion region that around both sources 23 and drains 24. Therefore, owing to high electrical field may induce quantities of heat, it is possible that parasitic diodes are overburning by heat before so-called parasitic bipolar junction transistors are triggered, and then ESD protection circuit can not properly protect chips inside integrated circuits, even parasitic bipolar junction transistors are triggered later.
In summary, because conventional MOS ESD protection circuit faces the issue that parasitic diodes are destroyed before parasitic bipolar junction transistors are triggered, it is desired to modify structure of MOS ESD protection circuit to make sure that internal chips are properly protect since chargers appear on terminal, no matter parasitic bipolar junction transistors are trigger or not.